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features applications description ads8406 slas426a ? august 2004 ? revised december 2004 16-bit, 1.25 msps, pseudo-bipolar, fully differential input, micro power sampling analog-to-digital converter with parallel interface dwdm pseudo-bipolar, fully differential input, -v ref to v ref instrumentation high-speed, high-resolution, zero latency 16-bit nmc at 1.25 msps data acquisition systems 2 lsb inl max, -1/+1.25 lsb dnl transducer interface 90 db snr, -95 db thd at 100 khz input medical instruments zero latency communications internal 4.096 v reference high-speed parallel interface single 5 v analog supply the ads8406 is a 16-bit, 1.25 mhz a/d converter wide i/o supply: 2.7 v to 5.25 v with an internal 4.096-v reference. the device in- cludes a 16-bit capacitor-based sar a/d converter low power: 155 mw at 1.25 mhz typ with inherent sample and hold. the ads8406 offers a pin compatible with ads8412/8402 full 16-bit interface and an 8-bit option where data is 48-pin tqfp package read using two 8-bit read cycles. the ads8406 has a pseudo-bipolar, fully differential input. it is available in a 48-lead tqfp package and is characterized over the industrial -40 c to 85 c temperature range. high speed sar converter family type/speed 500 khz 580 khz 750 mhz 1.25 mhz 2 mhz 3 mhz 4 mhz 18 bit pseudo-diff ads8383 ads8381 ads8371 ads8401 ads8411 16 bit pseudo-diff ads8405 ads8402 ads8412 16 bit pseudo bipolar, fully differential ads8406 14 bit pseudo-diff ads7890 (s) ads7891 12 bit pseudo-diff ads7881 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. production data information is current as of publication date. copyright ? 2004, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
cdac _ + output latches and 3-state drivers byte16-/8-bit parallel da t a output bus sar conversion and control logic comparator clock +in ?in refin convst busy cs rd reset 4.096-v internal reference refout
absolute maximum ratings ads8406 slas426a ? august 2004 ? revised december 2004 ordering information (1) maximum maximum no missing package tempera- transport integral differential codes package ordering model desig- ture media linearity linearity resolution type information nator range quantity (lsb) (lsb) (bit) tape and reel ads8406ipfbt 250 48 pin ads8406i ?4 to +4 ?2 to +2 15 pfb ?40 c to 85 c tqfp tape and reel ads8406ipfbr 1000 tape and reel ads8406ibpfbt 250 48 pin ads8406ib ?2 to +2 ?1 to +1.25 16 pfb ?40 c to 85 c tqfp tape and reel ads8406ibpfbr 1000 (1) for the most current specifications and package information, refer to our website at www.ti.com. over operating free-air temperature range unless otherwise noted (1) unit +in to agnd ?0.4 v to +va + 0.1 v voltage ?in to agnd ?0.4 v to +va + 0.1 v +va to agnd ?0.3 v to 7 v voltage range +vbd to bdgnd ?0.3 v to 7 v +va to +vbd ?0.3 v to 2.55 v digital input voltage to bdgnd ?0.3 v to +vbd + 0.3 v digital output voltage to bdgnd ?0.3 v to +vbd + 0.3 v t a operating free-air temperature range ?40 c to 85 c t stg storage temperature range ?65 c to 150 c junction temperature (t j max) 150 c power dissipation (t j max - t a )/ q ja tqfp package q ja thermal impedance 86 c/w vapor phase (60 sec) 215 c lead temperature, soldering infrared (15 sec) 220 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 www .ti.com
specifications ads8406 slas426a ? august 2004 ? revised december 2004 t a = ?40 c to 85 c, +va = 5 v, +vbd = 3 v or 5 v, v ref = 4.096 v, f sample = 1.25 mhz (unless otherwise noted) parameter test conditions min typ max unit analog input full-scale input voltage (1) +in ? (?in) ?v ref v ref v +in ?0.2 v ref + 0.2 absolute input voltage v ?in ?0.2 v ref + 0.2 input capacitance 25 pf input leakage current 0.5 na system performance resolution 16 bits ads8406i 15 no missing codes bits ads8406ib 16 ads8406i ?4 2 4 inl integral linearity (2) (3) lsb ads8406ib ?2 1 2 ads8406i ?2 1 2 dnl differential linearity lsb ads8406ib ?1 0.5 1.25 ads8406i ?2.5 1 2.5 mv e o offset error (4) ads8406ib ?1.5 0.5 1.5 mv ads8406i ?0.12 0.12 e g gain error (4) (5) %fs ads8406ib ?0.098 0.098 at dc (0.2 v around v ref /2) 80 cmrr common mode rejection ratio db +in ? (?in) = 1 v pp at 1 mhz 80 at 7fffh output code, +va psrr dc power supply rejection ratio = 4.75 v to 5.25 v, v ref = 2 lsb 4.096 v (4) sampling dynamics conversion time 500 650 ns acquisition time 150 ns throughput rate 1.25 mhz aperture delay 2 ns aperture jitter 25 ps step response 100 ns overvoltage recovery 100 ns dynamic characteristics v in = 8 v pp at 100 khz ?95 thd total harmonic distortion (6) db v in = 8 v pp at 500 khz ?90 snr signal-to-noise ratio v in = 8 v pp at 100 khz 90 db sinad signal-to-noise + distortion v in = 8 v pp at 100 khz 88 db v in = 8 v pp at 100 khz 95 sfdr spurious free dynamic range db v in = 8 v pp at 500 khz 93 -3db small signal bandwidth 5 mhz external voltage reference input reference voltage at refin, v ref 2.5 4.096 4.2 v reference resistance (7) 500 k w (1) ideal input span, does not include gain or offset error. (2) lsb means least significant bit (3) this is endpoint inl, not best fit. (4) measured relative to an ideal full-scale input [+in ? (?in)] of 8.192 v (5) this specification does not include the internal reference voltage error and drift. (6) calculated on the first nine harmonics of the input frequency (7) can vary 20% 3 www .ti.com
ads8406 slas426a ? august 2004 ? revised december 2004 specifications (continued) t a = ?40 c to 85 c, +va = 5 v, +vbd = 3 v or 5 v, v ref = 4.096 v, f sample = 1.25 mhz (unless otherwise noted) parameter test conditions min typ max unit internal reference output from 95% (+va) with 1-f internal reference start-up time 120 ms storage capacitor v ref reference voltage iout = 0 4.065 4.096 4.13 v source current static load 10 a line regulation +va = 4.75 to 5.25 v 0.6 mv drift iout = 0 36 ppm/ c digital input/output logic family ? cmos v ih high level input voltage i ih = 5 a +vbd ? 1 +vbd + 0.3 v il low level input voltage i il = 5 a ?0.3 0.8 v v oh high level output voltage i oh = 2 ttl loads +vbd ? 0.6 +vbd v ol low level output voltage i ol = 2 ttl loads 0 0.4 data format ? 2's complement power supply requirements +vbd 2.7 3 5.25 v power supply voltage +va 4.75 5 5.25 v supply current, +va (8) f s = 1.25 mhz 31 34 ma p d power dissipation (8) f s = 1.25 mhz 155 170 mw temperature range t a operating free-air temperature ?40 85 c (8) this includes only +va current. +vbd current is typically 1 ma with 5-pf load capacitance on output pins. 4 www .ti.com
timing characteristics ads8406 slas426a ? august 2004 ? revised december 2004 all specifications typical at ?40 c to 85 c, +va = +vbd = 5 v (1) (2) (3) parameter min typ max unit t conv conversion time 500 650 ns t acq acquisition time 150 ns t pd1 convst low to busy high 40 ns t pd2 propagation delay time, end of conversion to busy low 5 ns t w1 pulse duration, convst low 20 ns t su1 setup time, cs low to convst low 0 ns t w2 pulse duration, convst high 20 ns convst falling edge jitter 10 ps t w3 pulse duration, busy signal low min(t acq ) ns t w4 pulse duration, busy signal high 610 ns hold time, first data bus data transition ( rd low, or cs low for t h1 40 ns read cycle, or byte input changes) after convst low delay time, cs low to rd low (or busy low to rd low when cs = t d1 0 ns 0) t su2 setup time, rd high to cs high 0 ns t w5 pulse duration, rd low time 50 ns t en enable time, rd low (or cs low for read cycle) to data valid 20 ns t d2 delay time, data hold from rd high 0 ns t d3 delay time, byte rising edge or falling edge to data valid 2 20 ns t w6 pulse duration, rd high 20 ns t w7 pulse duration, cs high time 20 ns hold time, last rd (or cs for read cycle ) rising edge to convst t h2 50 ns falling edge t su3 setup time, byte transition to rd falling edge 0 ns t h3 hold time, byte transition to rd falling edge 0 ns disable time, rd high ( cs high for read cycle) to 3-stated data t dis 20 ns bus t d5 delay time, end of conversion to msb data valid 10 ns byte transition setup time, from byte transition to next byte t su4 50 ns transition t d6 delay time, cs rising edge to busy falling edge 50 ns t d7 delay time, busy falling edge to cs rising edge 50 ns setup time, from the falling edge of convst (used to start the valid conversion) to the next falling edge of convst (when cs = t su(ab) 60 500 ns 0 and convst used to abort) or to the next falling edge of cs (when cs is used to abort) setup time, falling edge of convst to read valid data (msb) from t su5 max(t conv ) + max(t d5 ) ns current conversion hold time, data (msb) from previous conversion hold valid from t h4 min(t conv ) ns falling edge of convst (1) all input signals are specified with t r = t f = 5 ns (10% to 90% of +vbd) and timed from a voltage level of (v il + v ih )/2. (2) see timing diagrams. (3) all timings are measured with 20-pf equivalent loads on all data bits and busy pins. 5 www .ti.com
timing characteristics ads8406 slas426a ? august 2004 ? revised december 2004 all specifications typical at ?40 c to 85 c, +va = 5 v, +vbd = 3 v (1) (2) (3) parameter min typ max unit t conv conversion time 500 650 ns t acq acquisition time 150 ns t pd1 convst low to busy high 50 ns t pd2 propagation delay time, end of conversion to busy low 10 ns t w1 pulse duration, convst low 20 ns t su1 setup time, cs low to convst low 0 ns t w2 pulse duration, convst high 20 ns convst falling edge jitter 10 ps t w3 pulse duration, busy signal low min(t acq ) ns t w4 pulse duration, busy signal high 610 ns hold time, first data bus transition ( rd low, or cs low for read t h1 40 ns cycle, or byte or bus 16/ 16 input changes) after convst low delay time, cs low to rd low (or busy low to rd low when cs = t d1 0 ns 0) t su2 setup time, rd high to cs high 0 ns t w5 pulse duration, rd low 50 ns t en enable time, rd low (or cs low for read cycle) to data valid 30 ns t d2 delay time, data hold from rd high 0 ns t d3 delay time, byte rising edge or falling edge to data valid 2 30 ns t w6 pulse duration, rd high time 20 ns t w7 pulse duration, cs high time 20 ns hold time, last rd (or cs for read cycle ) rising edge to convst t h2 50 ns falling edge t su3 setup time, byte transition to rd falling edge 0 ns t h3 hold time, byte transition to rd falling edge 0 ns t dis disable time, rd high ( cs high for read cycle) to 3-stated data bus 30 ns t d5 delay time, end of conversion to msb data valid 20 ns byte transition setup time, from byte transition to next byte t su4 50 ns transition t d6 delay time, cs rising edge to busy falling edge 50 ns t d7 delay time, busy falling edge to cs rising edge 50 ns setup time, from the falling edge of convst (used to start the valid conversion) to the next falling edge of convst (when cs = 0 t su(ab) 70 500 ns and convst used to abort) or to the next falling edge of cs (when cs is used to abort) setup time, falling edge of convst to read valid data (msb) from t su5 max(t conv ) + max(t d5 ) ns current conversion hold time, data (msb) from previous conversion hold valid from t h4 min(t conv ) ns falling edge of convst (1) all input signals are specified with t r = t f = 5 ns (10% to 90% of +vbd) and timed from a voltage level of (v il + v ih )/2. (2) see timing diagrams. (3) all timings are measured with 20-pf equivalent loads on all data bits and busy pins. 6 www .ti.com
pin assignments ads8406 slas426a ? august 2004 ? revised december 2004 7 www .ti.com 1 1 nc - no connection +vbddb8 db9 db10 db1 1 db12db13 db14 db15 agnd agnd +v a 1 2 3738 39 40 41 42 43 44 45 46 47 48 +vbd reset byte convst rd cs +v a agndagnd +v a refmrefm 3 4 5 6 pfb p ackage (t op view) db4 db5 db6 db7 35 34 33 32 31 36 30 busybdgnd +vbd db0 db1 db2 db3 agnd +v a +v a refin refout nc +v a agnd +in -in 28 27 26 29 7 8 9 10 agnd 2423 22 21 20 19 18 17 16 15 14 13 agnd 12 bdgnd 25
ads8406 slas426a ? august 2004 ? revised december 2004 terminal functions name no. i/o description agnd 5, 8, 11, 12, 14, ? analog ground 15, 44, 45 bdgnd 25, 35 ? digital ground for bus interface digital supply busy 36 o status output. high when a conversion is in progress. byte 39 i byte select input. used for 8-bit bus reading. 0: no fold back 1: low byte d[7:0] of the 16 most significant bits is folded back to high byte of the 16 most significant pins db[15:8]. convst 40 i convert start. the falling edge of this input ends the acquisition period and starts the hold period. cs 42 i chip select. the falling edge of this input starts the acquisition period. 8-bit bus 16-bit bus data bus byte = 0 byte = 1 byte = 0 db15 16 o d15 (msb) d7 d15 (msb) db14 17 o d14 d6 d14 db13 18 o d13 d5 d13 db12 19 o d12 d4 d12 db11 20 o d11 d3 d11 db10 21 o d10 d2 d10 db9 22 o d9 d1 d9 db8 23 o d8 d0 (lsb) d8 db7 26 o d7 all ones d7 db6 27 o d6 all ones d6 db5 28 o d5 all ones d5 db4 29 o d4 all ones d4 db3 30 o d3 all ones d3 db2 31 o d2 all ones d2 db1 32 o d1 all ones d1 db0 33 o d0 (lsb) all ones d0 (lsb) ?in 7 i inverting input channel +in 6 i non inverting input channel nc 3 ? no connection refin 1 i reference input refm 47, 48 i reference ground refout 2 o reference output. add 1-f capacitor between the refout pin and refm pin when internal reference is used. reset 38 i current conversion is aborted and output latches are cleared (set to zeros) when this pin is asserted low. reset works independantly of cs. rd 41 i synchronization pulse for the parallel output. when cs is low, this serves as the output enable and puts the previous conversion result on the bus. +va 4, 9, 10, 13, 43, ? analog power supplies, 5-v dc 46 +vbd 24, 34, 37 ? digital power supply for bus 8 www .ti.com
timing diagrams ads8406 slas426a ? august 2004 ? revised december 2004 figure 1. timing for conversion and acquisition cycles with cs and rd toggling 9 www .ti.com t w 1 convst t p d 1 t p d 2 t w 4 t s u 1 busy cs convert 2 t c o n v sampling 2 (when cs t oggle) byte t w 2 t w 3 t a c q t h 1 t d 1 t e n rd t d i s t h 2 t s u 2 t c o n v 2 signal internal to device d [7:0] hi?z hi?z db[15:8] hi?z hi?z d [15:8] d [7:0] db[7:0] t d 6 t s u 4 t w 7 t d 7 t c y c l e t p d 1 data tobe read 2 invalid previous conversion current conversion invalid t h 4 t s u 5 (used in normalconversion) convst (used in abort) t s u ( a b ) t s u ( a b )
ads8406 slas426a ? august 2004 ? revised december 2004 timing diagrams (continued) figure 2. timing for conversion and acquisition cycles with cs toggling, rd tied to bdgnd 10 www .ti.com 2 signal internal to device convst busy cs convert 2 sampling 2 (when cs t oggle) byte rd = 0 t w 1 t p d 1 t p d 2 t w 4 t w 2 t w 3 t s u 1 t c o n v t a c q t c o n v t h 1 t e n t h 2 t d i s d [7:0] hi?z hi?z db[15:8] hi?z hi?z d [15:8] d [7:0] db[7:0] t d 6 t s u 4 t w 7 t d 7 d [15:8] d [7:0] t d i s hi?z hi?z t e n d [15:8] d [7:0] t e n previousprevious repeatedrepeated t c y c l e t s u ( a b ) t s u ( a b ) (used in normalconversion) convst (used in abort) data tobe read 2 invalid invalid t h 4 t s u 5 previous conversion current conversion
ads8406 slas426a ? august 2004 ? revised december 2004 timing diagrams (continued) figure 3. timing for conversion and acquisition cycles with cs tied to bdgnd, rd toggling 11 www .ti.com 2 signal internal to device t c o n v convst busy cs = 0 convert 2 sampling 2 (when cs = 0) byte rd t w 1 t p d 2 t p d 1 t w 4 t w 2 t w 3 t c o n v t ( a c q ) t h 1 t h 2 t e n t d i s d [7:0] hi?z hi?z db[15:8] hi?z hi?z d [15:8] d [7:0] db[7:0] t s u 4 t c y c l e t s u ( a b ) t s u ( a b ) convst (used in abort) (used in normalconversion) t p d 1 data tobe read 2 invalid invalid t h 4 t s u 5 previous conversion current conversion
ads8406 slas426a ? august 2004 ? revised december 2004 timing diagrams (continued) figure 4. timing for conversion and acquisition cycles with cs and rd tied to bdgnd?auto read figure 5. detailed timing for read cycles 12 www .ti.com 2 signal internal to device convst busy cs = 0 convert 2 sampling 2 (when cs t oggle) byte rd = 0 t w 1 t p d 1 t p d 2 t w 4 t w 2 t w 3 t c o n v t a c q t c o n v invalid db[15:8] db[7:0] msb lsb t d 3 previous previous t c y c l e t s u ( a b ) t s u ( a b ) (used in normalconversion) convst (used in abort) t s u 5 t p d 2 t h 1 t h 1 t p d 1 t d 3 t d 3 t h 4 lsb previous t d 5 invalid msb msb msb msb invalid invalid lsb t h 4 t d 5 t s u 5 lsb v alid hi?z t e n t d i s t e n t d 3 t d i s v alid v alid hi?z hi?z cs rd byte db[15:0] t s u 4
typical characteristics ads8406 slas426a ? august 2004 ? revised december 2004 at ?40 c to 85 c, +va = 5 v, +vbd = 5 v, refin = 4.096 v (internal reference used) and f sample = 1.25 mhz (unless otherwise noted) signal-to-noise ratio histogram (dc code spread) vs half scale 131071 conversions free-air temperature figure 6. figure 7. signal-to-noise and distortion effective number of bits vs vs free-air temperature free-air temperature figure 8. figure 9. 13 www .ti.com snr ? signal-to-noise ratio ? db t a ? free-air t emperature ? c 90.3 90.4 90.5 90.6 90.7 90.8 90.9 ?40 ?25 ?10 5 20 35 50 65 80 f i = 50 khz, full scale input,v a = 5 v , vbd = 3 v , internal reference = 4.096 v 0 10000 20000 30000 40000 50000 60000 70000 80000 65295 65292 65289 +v a = 5 v , +vbd = 3.3 v , t a = 25 c, code = 65292 sinad ? signal-to-noise and distortion ? db t a ? free-air t emperature ? c 89 89.5 90 90.5 91 ?40 ?25 ?10 5 20 35 50 65 80 f i = 50 khz, full scale input,v a = 5 v , vbd = 3 v , internal reference = 4.096 v enob ? effective number of bits ? bits t a ? free-air t emperature ? c 14.4 14.5 14.6 14.7 14.8 ?40 ?25 ?10 5 20 35 50 65 80 f i = 50 khz, full scale input,v a = 5 v , vbd = 3 v , internal reference = 4.096 v
ads8406 slas426a ? august 2004 ? revised december 2004 typical characteristics (continued) spurious free dynamic range total harmonic distortion vs vs free-air temperature free-air temperature figure 10. figure 11. signal-to-noise ratio effective number of bits vs vs input frequency input frequency figure 12. figure 13. signal-to-noise and distortion spurious free dynamic range vs vs input frequency input frequency figure 14. figure 15. 14 www .ti.com t a ? free-air t emperature ? c thd ? t otal harmonic distortion ? db ?102 ?101 ?100 ?99 ?98 ?97 ?96 ?95 ?94 ?40 ?25 ?10 5 20 35 50 65 80 f i = 50 khz, full scale input,v a = 5 v , vbd = 3 v , internal reference = 4.096 v t a ? free-air t emperature ? c sfdr ? spurious free dynamic range ? db 94 95 96 97 98 99 100 101 102 ?40 ?25 ?10 5 20 35 50 65 80 f i = 50 khz, full scale input,v a = 5 v , vbd = 3 v , internal reference = 4.096 v snr ? signal-to-noise ratio ? db f i ? input frequency ? khz 89.8 90 90.2 90.4 90.6 90.8 91 91.2 91.4 91.6 91.8 92 0 10 20 30 40 50 60 70 80 90 100 full scale input,v a = 5 v , vbd = 5 v , t a = 25 c, internal reference = 4.096 v 14.4 14.5 14.6 14.7 14.8 14.9 0 10 20 30 40 50 60 70 80 90 100 full scale input,v a = 5 v , vbd = 5 v , t a = 25 c, internal reference = 4.096 v enob ? effective number of bits ? bits f i ? input frequency ? khz 88.5 89 89.5 90 90.5 91 91.5 0 10 20 30 40 50 60 70 80 90 100 f i ? input frequency ? khz sinad ? signal-to-noise and distortion ? db full scale input,v a = 5 v , vbd = 5 v , t a = 25 c, internal reference = 4.096 v f i ? input frequency ? khz sfdr ? spurious free dynamic range ? db 94 95 96 97 98 99 100 101 0 10 20 30 40 50 60 70 80 90 100 full scale input,v a = 5 v , vbd = 5 v , t a = 25 c, internal reference = 4.096 v
ads8406 slas426a ? august 2004 ? revised december 2004 typical characteristics (continued) total harmonic distortion supply current vs vs input frequency sample rate figure 16. figure 17. gain error offset error vs vs supply voltage supply voltage figure 18. figure 19. internal voltage reference gain error vs vs free-air temperature free-air temperature figure 20. figure 21. 15 www .ti.com f i ? input frequency ? khz thd ? t otal harmonic distortion ? db ?101 ?100 ?99 ?98 ?97 ?96 ?95 ?94 0 10 20 30 40 50 60 70 80 90 100 full scale input,v a = 5 v , vbd = 5 v , t a = 25 c, internal reference = 4.096 v 26.5 27 27.5 28 28.5 29 29.5 30 30.5 250 500 750 1000 1250 i cc ? supply current ? ma throughput ? ksps t a = 25 c, current of +v a only , vbd = 5 v , v a = 5 v ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 4.75 5 5.25 t a = 25 c, external reference = 4.096 v , vbd = 5 v gain error ? mv v c c ? supply v oltage ? v 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 4.75 5 5.25 t a = 25 c, external reference = 4.096 v , vbd = 5 v offset v oltage ? mv v c c ? supply v oltage ? v ?40 ?25 ?10 5 20 35 50 65 80 1.5 1 0.5 0 ?0.5 ?1 ?1.5 external refence = 4.096 v , vbd = 5 v , v a = 5 v gain error ? mv t a ? free-air t emperature ? c 4.086 4.088 4.09 4.092 4.094 4.096 4.098 4.1 ?40 ?25 ?10 5 20 35 50 65 80 vbd = 5 v , v a = 5 v t a ? free-air t emperature ? c internal reference output ? v
ads8406 slas426a ? august 2004 ? revised december 2004 typical characteristics (continued) offset error supply current vs vs free-air temperature free-air temperature figure 22. figure 23. differential nonlinearity integral nonlinearity vs vs free-air temperature free-air temperature figure 24. figure 25. differential nonlinearity integral nonlinearity vs vs reference voltage reference voltage figure 26. figure 27. 16 www .ti.com 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 ?40 ?25 ?10 5 20 35 50 65 80 external reference = 4.096 v , vbd = 5 v , v a = 5 v t a ? free-air t emperature ? c offset v oltage ? mv 28.8 29 29.2 29.4 29.6 29.8 30 30.2 30.4 ?40 ?25 ?10 5 20 35 50 65 80 t a ? free-air t emperature ? c i cc ? supply current ? ma external reference = 4.096 v , current of +v a only , vbd = 5 v , v a = 5 v t a ? free-air t emperature ? c dnl ? differential nonlinearity ? bits ?1.5 ?1 ?0.5 0 0.5 1 1.5 ?40 ?25 ?10 5 20 35 50 65 80 max min external reference = 4.096 v , vbd = 5 v , v a = 5 v t a ? free-air t emperature ? c inl ? integral nonlinearity ? bits ?1.5 ?1 ?0.5 0 0.5 1 1.5 ?40 ?25 ?10 5 20 35 50 65 80 max min external reference = 4.096 v , vbd = 5 v , v a = 5 v dnl ? differential nonlinearity ? bits ?2 ?1.5 ?1 ?0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 v r e f ? reference v oltage ? v t a = 25 c, v a = 5 v , vbd = 5 v max min ?2 ?1.5 ?1 ?0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 inl ? integral nonlinearity ? bits max min v r e f ? reference v oltage ? v t a = 25 c, v a = 5 v , vbd = 5 v
ads8406 slas426a ? august 2004 ? revised december 2004 typical characteristics (continued) dnl figure 28. inl figure 29. fft figure 30. 17 www .ti.com 0 16384 32768 49152 65536 code 0 0.5 1.5 2 2.5 ?0.5 ?1?2 ?2.5 dnl ? lsbs ?1.5 1 0 16384 32768 49152 65536 code 0 0.5 1.5 2 2.5 ?0.5 ?1?2 ?2.5 inl ? lsbs ?1.5 1 ?200 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 100 k 200 k 300 k 400 k 500 k 600 k amplitude samples f i = 100 khz, f s = 1.25 mhz, t a = 25 c, internal reference = 4.096 v
application information microcontroller interfacing ads8406 to 8-bit microcontroller interface principles of operation ads8406 slas426a ? august 2004 ? revised december 2004 figure 31 shows a parallel interface between the ads8406 and a typical microcontroller using the 8-bit data bus. the busy signal is used as a falling-edge interrupt to the microcontroller. figure 31. ads8406 application circuitry (using external reference) figure 32. use internal reference the ads8406 is a high-speed successive approximation register (sar) analog-to-digital converter (adc). the architecture is based on charge redistribution, which inherently includes a sample/hold function. see figure 31 for the application circuit for the ads8406. the conversion clock is generated internally. the conversion time of 650 ns is capable of sustaining a 1.25-mhz throughput. 18 www .ti.com cs rd convst busy bdgnd +vbd db[15:8] micro controller rd gpio int 10 m f 0.1 m f analog 5 v 0.1 m f digital 3 v ext ref inputanalog input +v a refm agnd +in ?in ads8406 0.1 m f refin 1 m f agnd bdgnd gpio byte p[7:0] gpio +v a refout refin refm agnd 0.1 m f 1 m f 0.1 m f 10 m f analog 5 v ads8406 agnd agnd
reference analog input ads8406 slas426a ? august 2004 ? revised december 2004 principles of operation (continued) the analog input is provided to two input pins: +in and ?in. when a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. while a conversion is in progress, both inputs are disconnected from any internal function. the ads8406 can operate with an external reference with a range from 2.5 v to 4.2 v. a 4.096-v internal reference is included. when internal reference is used, pin 2 (refout) should be connected to pin 1 (refin) with a 0.1-f decoupling capacitor and 1-f storage capacitor between pin 2 (refout) and pins 47 and 48 (refm) (see figure 33). the internal reference of the converter is double buffered. if an external reference is used, the second buffer provides isolation between the external reference and the cdac. this buffer is also used to recharge all of the capacitors of the cdac during conversion. pin 2 (refout) can be left unconnected (floating) if external reference is used. when the converter enters the hold mode, the voltage difference between the +in and -in inputs is captured on the internal capacitor array. both +in and ?in inputs have a range of ?0.2 v to v ref + 0.2 v. the input span (+in ? (?in)) is limited to -v ref to v ref .. the input current on the analog inputs depends upon a number of factors: sample rate, input voltage, and source impedance. essentially, the current into the ads8406 charges the internal capacitor array during the sample period. after this capacitance has been fully charged, there is no further input current. the source of the analog input voltage must be able to charge the input capacitance (25 pf) to an 16-bit settling level within the acquisition time (150 ns) of the device. when the converter goes into the hold mode, the input impedance is greater than 1 g w . care must be taken regarding the absolute analog input voltage. to maintain the linearity of the converter, the +in and ?in inputs and the span (+in ? (?in)) should be within the limits specified. outside of these ranges, the converter's linearity may not meet specifications. to minimize noise, low bandwidth input signals with low-pass filters should be used. care should be taken to ensure that the output impedance of the sources driving +in and ?in inputs are matched. if this is not observed, the two inputs could have different setting time. this may result in offset error, gain error and linearity error which varies with temperature and input voltage. a typical input circuit using ti's ths4503 is shown in figure 33 . input from a single-ended source may be converted into a differential signal for the ads8406 as shown in the figure. in case the source itself is differential, then the ths4503 may be used in differential input and differential output modes. figure 33. using the ths4503 with the ads8406 19 www .ti.com _ + _ + in?in+ ads8406 _ + v c c + v c c ? 1 k w 1 k w ths4503 68 pf 68 pf 50 w 50 w 20 pf r g r s r t ocm 1 k w r g , r s , and r t should be chosen such that r g + r s || r t = 1 k w v o c m = 2 v , +v c c = 7 v , and ?v c c = ?7 v
digital interface timing and control reading data ads8406 slas426a ? august 2004 ? revised december 2004 principles of operation (continued) see the timing diagrams in the specifications section for detailed information on timing signals and their requirements. the ads8406 uses an internal oscillator generated clock which controls the conversion rate and in turn the throughput of the converter. no external clock input is required. conversions are initiated by bringing the convst pin low for a minimum of 20 ns (after the 20 ns minimum requirement has been met, the convst pin can be brought high), while cs is low. the ads8406 switches from the sample to the hold mode on the falling edge of the convst command. a clean and low jitter falling edge of this signal is important to the performance of the converter. the busy output is brought high after convst goes low. busy stays high throughout the conversion process and returns low when the conversion has ended. sampling starts as soon as the conversion is over when cs is tied low or starts with the falling edge of cs when busy is low. both rd and cs can be high during and before a conversion with one exception ( cs must be low when convst goes low to initiate a conversion). both the rd and cs pins are brought low in order to enable the parallel output bus with the conversion. the ads8406 outputs full parallel data in two's complement format as shown in table 1 . the parallel output is active when cs and rd are both low. there is a minimal quiet zone requirement around the falling edge of convst. this is 50 ns prior to the falling edge of convst and 40 ns after the falling edge. no data read should be attempted within this zone. any other combination of cs and rd sets the parallel output to 3-state. byte is used for multiword read operations. byte is used whenever lower bits of the converter result are output on the higher byte of the bus. refer to table 1 for ideal output codes. table 1. ideal input voltages and output codes description analog value digital output full scale range 2(+v ref ) 2's complement least significant bit (lsb) 2(+v ref )/65536 binary code hex code +full scale (+v ref ) ? 1 lsb 0111 1111 1111 1111 7fff midscale 0 v 0000 0000 0000 0000 0000 midscale ? 1 lsb 0 v? 1 lsb 1111 1111 1111 1111 ffff ? full scale ( ?v ref ) 1000 0000 0000 0000 8000 the output data is a full 16-bit word (d15?d0) on db15?db0 pins (msb?lsb) if byte is low. the result may also be read on an 8-bit bus for convenience. this is done by using only pins db15?db8. in this case two reads are necessary: the first as before, leaving byte low and reading the 8 most significant bits on pins db15?db8, then bringing byte high. when byte is high, the low bits (d7?d0) appear on pins db15?d8. these multiword read operations can be done with multiple active rd (toggling) or with rd tied low for simplicity. conversion data readout data read out byte db15?db8 pins db7?db0 pins high d7?d0 all one's low d15?d8 d7?d0 20 www .ti.com
reset power-on initialization layout ads8406 slas426a ? august 2004 ? revised december 2004 reset is an asynchronous active low input signal (that works independently of cs). minimum reset low time is 25 ns. current conversion will be aborted no later than 50 ns after the converter is in the reset mode. in addition, all output latches are cleared (set to zero's) after reset. the converter goes back to normal operation mode no later than 20 ns after reset input is brought high. the converter starts the first sampling period 20 ns after the rising edge of reset. any sampling period except for the one immediately after a reset is started with the falling edge of the previous busy signal or the falling edge of cs, whichever is later. another way to reset the device is through the use of the combination of cs and convst. this is useful when the dedicated reset pin is tied to the system reset but there is a need to abort only the conversion in a specific converter. since the busy signal is held high during the conversion, either one of these conditions triggers an internal self-clear reset to the converter just the same as a reset via the dedicated reset pin. the reset does not have to be cleared as for the dedicated reset pin. a reset can be started with either of the two following steps. issue a convst when cs is low and a conversion is in progress. the falling edge of convst must satisfy the timing as specified by the timing parameter t su(ab) mentioned in the timing characteristics table to ensure a reset. the falling edge of convst starts a reset. timing is the same as a reset using the dedicated reset pin except the instance of the falling edge is replaced by the falling edge of convst. issue a cs while a conversion is in progress. the falling edge of cs must satisfy the timing as specified by the timing parameter t su(ab) mentioned in the timing characteristics table to ensure a reset.the falling edge of cs causes a reset. timing is the same as a reset using the dedicated reset pin except the instance of the falling edge is replaced by the falling edge of cs. reset is not required after power on. an internal power-on-reset circuit generates the reset. to ensure that all of the registers are cleared, the three conversion cycles must be given to the converter after power on. for optimum performance, care should be taken with the physical layout of the ads8406 circuitry. as the ads8406 offers single-supply operation, it is often used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. the more digital logic present in the design and the higher the switching speed, the more difficult it is to achieve good performance from the converter. the basic sar architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections and digital inputs that occur just prior to latching the output of the analog comparator. thus, driving any single conversion for an n-bit sar converter, there are at least n windows in which large external transient voltages can affect the conversion result. such glitches might originate from switching power supplies, nearby digital logic, or high power devices. the degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. on average, the ads8406 draws very little current from an external reference, as the reference voltage is internally buffered. if the reference voltage is external and originates from an op amp, make sure that it can drive the bypass capacitor or capacitors without oscillation. a 0.1-f bypass capacitor and a 1-f storage capacitor are recommended from pin 1 (refin) directly to pin 48 (refm). refm and agnd should be shorted on the same ground plane under the device. the agnd and bdgnd pins should be connected to a clean ground point. in all cases, this should be the analog ground. avoid connections which are close to the grounding point of a microcontroller or digital signal processor. if required, run a ground trace directly from the converter to the power supply entry point. the ideal layout consists of an analog ground plane dedicated to the converter and associated analog circuitry. 21 www .ti.com
ads8406 slas426a ? august 2004 ? revised december 2004 as with the agnd connections, +va should be connected to a 5-v power supply plane or trace that is separate from the connection for digital logic until they are connected at the power entry point. power to the ads8406 should be clean and well bypassed. a 0.1-f ceramic bypass capacitor should be placed as close to the device as possible. see table 2 for the placement of the capacitor. in addition, a 1-f to 10-f capacitor is recommended. in some situations, additional bypassing may be required, such as a 100-f electrolytic capacitor or even a pi filter made up of inductors and capacitors?all designed to essentially low-pass filter the 5-v supply, removing the high frequency noise. table 2. power supply decoupling capacitor placement power supply plane converter analog side converter digital side supply pins (4,5), (8,9), (10,11), (13,15), pin pairs that require shortest path to decoupling capacitors (24,25), (34, 35) (43,44), (45,46) pins that require no decoupling 12, 14 37 22 www .ti.com
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) ads8406ibpfbr active tqfp pfb 48 2000 none cu nipdau level-2-220c-1 year ads8406ibpfbt active tqfp pfb 48 250 none cu nipdau level-2-220c-1 year ads8406ipfbr active tqfp pfb 48 2000 none cu nipdau level-2-220c-1 year ads8406ipfbt active tqfp pfb 48 250 none cu nipdau level-2-220c-1 year (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - may not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. none: not yet available lead (pb-free). pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. green (rohs & no sb/br): ti defines "green" to mean "pb-free" and in addition, uses package materials that do not contain halogens, including bromine (br) or antimony (sb) above 0.1% of total product weight. (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedecindustry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 18-feb-2005 addendum-page 1
mechanical data mtqf019a january 1995 revised january 1998 post office box 655303 ? dallas, texas 75265 pfb (s-pqfp-g48) plastic quad flatpack 4073176 / b 10/96 gage plane 0,13 nom 0,25 0,45 0,75 seating plane 0,05 min 0,17 0,27 24 25 13 12 sq 36 37 7,20 6,80 48 1 5,50 typ sq 8,80 9,20 1,05 0,95 1,20 max 0,08 0,50 m 0,08 0 7 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security telephony www.ti.com/telephony video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2005, texas instruments incorporated

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